|
Class Summary |
| ALU |
This is a simple ALU processor. |
| ARC_demo |
This implements an 4x4 heterogeneous
processor array in a checkerboard pattern with
an ARC700 and extended ARC700EX processors. |
| ARC700 |
This is an AutoModel implementation of the ARC700
processor. |
| ARC700.BRCC |
|
| ARC700.CC |
|
| ARC700.OP |
|
| ARC700.REG |
This class defines some Register indicies |
| ARC700.SREG |
This class defines the Special Register indicies |
| ARC700EX |
This is an AutoModel implementation of the ARC700
processor with an extension. |
| AutoSimple |
This is the 'Simple' processor produced using the
AutoModel data-driven interface. |
| CellBE |
This implements the IBM / Toshiba / Sony
Cell Broadband Engine (CellBE). |
| Checkerboard |
This implements an 8x8 heterogeneous
processor array in a checkerboard pattern with
MIPS32 and Sparc-8 processors. |
| Default |
This implements the default array. |
| DualCellBE |
This implements a dual IBM / Toshiba / Sony
Cell Broadband Engine (CellBE) model. |
| FastSimple |
This is the 'Simple' processor produced using the
FastModel data-driven interface. |
| GdbTest |
This is a test for the GDB interface for the the IBM / Toshiba / Sony
Cell Broadband Engine (CellBE). |
| HardNodeDemo |
This gives an example of a HardNode. |
| Hetero |
This implements a demonstration heterogeneous
processor array. |
| LatticeMicro32 |
This is an AutoModel implementation of the LatticeMicro32
processor. |
| LatticeMicro32.REG |
This class defines some Register indicies |
| LatticeMicro32.SREG |
This class defines the Special Register indicies |
| LM32 |
This is just a renaming of the LatticeMicro32 model. |
| LM32_demo |
This implements the LM32 demo array. |
| MicroBlaze |
This implements the Xilinx Microblaze according to the
specification: "MicroBlaze Processor Reference Guide",
Embedded Development Kit EDK 9.1.i (UG081 9/15/2006) |
| MicroBlaze_old |
This implements the Xilinx Microblaze according to the
specification: "MicroBlaze Processor Reference Guide",
Embedded Development Kit EDK 6.3.i (UG081 August 24, 2004) |
| MIPS32 |
This is an AutoModel implementation of the MIPS32
processor. |
| MIPS32_demo |
This implements an 4x4 heterogeneous
processor array in a checkerboard pattern with
an MIPS32 and extended MIPS32EX processors. |
| MIPS32.SREG |
This class defines the Special Register indicies |
| MIPS32EX |
This is an AutoModel implementation of the MIPS32
processor with an extension. |
| NIOS |
This describes the Altera NIOS 32-bit CPU. |
| NIOS2 |
This is the model for the NIOS2 processor from Altera. |
| Null |
This class implements a "null" spacer processor model. |
| PowerPC |
This is an AutoModel implementation of the PowerPC
processor. |
| PowerPC_fp |
This is an implementation of the PowerPC floating point
instructions using the AutoModel approach. |
| PowerPC_fp.FCR0 |
This class defines the fields in the CR Special Register |
| PowerPC_fp.FPSCR |
This class defines the fields in the FPSCR Special Register |
| PowerPC.CR0 |
This class defines the fields in the CR Special Register |
| PowerPC.MSR |
This class defines the fields in the MSR Special Register |
| PowerPC.SR |
This class defines the Special Register indicies |
| PowerPC.XER |
This class defines the fields in the XER Special Register |
| PowerPC64 |
This is an AutoModel implementation of the PowerPC 64 bit
processor istructions. |
| PowerPC64.CR0 |
This class defines the fields in the CR Special Register |
| PowerPC64.MSR |
This class defines the fields in the MSR Special Register |
| PowerPC64.SR |
This class defines the Special Register indicies |
| PowerPC64.XER |
This class defines the fields in the XER Special Register |
| Sparc |
This is the model for the SPARC 8 processor. |
| Sparc.COND |
This class defines the bit filed constants for the
COND (condition code) opcode field |
| Sparc.OP |
This class defines the bit field constants for the OP3
opcode field |
| Sparc.OP2 |
This class defines the bit field constants for the OP2
opcode field |
| Sparc.OP3 |
This class defines the bit filed constants for the OP3
opcode field |
| Sparc.PSR |
This class defines Processor Status Register (PSR)
fields. |
| Sparc.SR |
This class defines the Special Registers |
| SPU |
This is an AutoModel implementation of the Synergistic
Processing Unit (SPU) used by the Cell broadband Engine. |
| SPU_pipeline |
This is part of the model for of the Synergistic
Processing Unit (SPU) used by the Cell broadband Engine. |
| SPU_pipeline.InstrData |
This class defines the pipeline properties for an instruction. |
| SPU.ADDR_OFFSET |
The Channel memory map address offsets |
| SPU.CHANNEL |
The Channel port numbers |
| SPURS |
This implements the Toshiba SPURS Engine based on the
Cell Broadband Engine (CellBE). |
| TestCustomArray |
This implements a demonstration heterogeneous
processor array. |
| VT_ECE_5530 |
This implements a 3 x 3 array of Xilinx MicroBlaze processors. |
| Xtensa |
This is an AutoModel implementation of the Tensilica Xtensa
processor. |
| Xtensa_demo |
This implements an 4x4 heterogeneous
processor array in a checkerboard pattern with
an Xtensa and extended XtensaEX processors. |
| Xtensa.SREG |
This class defines the Special Register indicies |
| XtensaEX |
This is an AutoModel implementation of the Xtensa
processor with an extension. |